例句與造句

1. Standard test access port and boundary scan architecture
   標(biāo)準(zhǔn)測試存取口及邊界掃描體系結(jié)構(gòu)
2. Application of boundary scan technique to the design for board - level test
   邊界掃描技術(shù)在板級可測性設(shè)計(jì)中的應(yīng)用
3. The article also addresses the mechanism of vector creation for boundary scan
   本文進(jìn)一步分析了邊界掃描測試矢量生成機(jī)制。
4. Boundary scan aims at the test of application system , e . g . pcb test
   邊界掃描測試是針對芯片的應(yīng)用系統(tǒng)進(jìn)行測試的，如pcb板測試。
5. As a kind of new developing bit technology , boundary scan technology is widely used in industry
   邊界掃描技術(shù)作為一種新興的bit技術(shù),在工業(yè)界內(nèi)得到了廣泛的應(yīng)用。
6. It's difficult to find boundary scan in a sentence. 用boundary scan造句挺難的
7. A plan of design for test based of boundary scan testing is introduced for this signal processing system
   接著，提出了該信號處理系統(tǒng)基于邊界掃描的可測性設(shè)計(jì)方案。
8. International standard ieee 1149 . 1 describes the basic circuit structure and performance of boundary scan
   國際標(biāo)準(zhǔn)ieee1149 . 1規(guī)定了邊界掃描的基本電路結(jié)構(gòu)和功能。
9. Jx5 microprocessor ’ s testing structure comprises built - in self - test ( bist ) , boundary scan and internal scan
   Jx5微處理器的測試結(jié)構(gòu)由bist 、邊界掃描和內(nèi)部掃描三部分組成。
10. In this paper , we combine the standard modules realize the boundary scan of estarl and also expand it to the test of internal circuit . this structure can save the i / o port of the chip and simplify the testing program
    本文結(jié)合標(biāo)準(zhǔn)模塊設(shè)計(jì)實(shí)現(xiàn)了estar1的邊界掃描結(jié)構(gòu)，并進(jìn)行了擴(kuò)展，應(yīng)用到芯片內(nèi)部測試，節(jié)約了測試i / o口消耗，簡化了測試過程。
11. In this paper we investigate and carry out boundary scan ^ internal scan and built - in self - test three dft technologies in the embedded microprocessor estarl and get satisfying result , the fault coverage is more than 96 %
    本文針對嵌入式微處理器estar1的結(jié)構(gòu)特點(diǎn)，研究并實(shí)現(xiàn)了邊界掃描、內(nèi)部全掃描和內(nèi)建自測試三種可測性設(shè)計(jì)技術(shù)，取得了良好的效果，故障覆蓋率達(dá)到96以上。
12. It is seen from the result of the experiment that pseudo exhaustive test with deltascan involvement is truly a simple and practical method to produce vectors for boundary scan , it is suitable for any kinds of boundary scan devices
    從試驗(yàn)結(jié)果可知，偽窮舉法與deltascan相結(jié)合的確是生成邊界掃描測試矢量的一個非常簡單實(shí)用的方法，適用于任何一種邊界掃描元件的測試矢量的生成。
13. There are a lot of methods available to create test vector . the thesis addresses their characteristics of the methods and special structure of boundary scan circuit respectively and come to a conclusion of pseudo - exchausive testing the most rational method applied to this situation
    測試矢量的生成方法很多，本文在研究了各種方法的特性，以及邊界掃描電路的特殊結(jié)構(gòu)后，采用了偽窮舉法生成測試矢量。
14. Not only the scan route solution , the built - in self - test solution and the boundary scan solution of design for testability are summarized , but also the applications and countermeasures of these 3 solutions are analysed and compared in details
    摘要綜述了超大規(guī)模集成電路的幾種主要的可測試性設(shè)計(jì)技術(shù)，如掃描路徑法、內(nèi)建自測試法和邊界掃描法等，并分析比較了這幾種設(shè)計(jì)技術(shù)各自的特點(diǎn)及其應(yīng)用方法和策略。
15. As one of the design for testability technology , boundary scan test ( bst ) fixes boundary scan cells between the device pins and core logics . thus , the bsc acts as the virtual test probe that carries out the test stimulus and captures the test response
    作為一種結(jié)構(gòu)插入的可測性技術(shù),邊界掃描測試( bst )技術(shù)將邊界掃描寄存器單元安插在集成電路內(nèi)部的每個引腳上,其作用相當(dāng)于設(shè)置了施加激勵和觀測響應(yīng)的內(nèi)建虛擬探頭。
16. Chapter two detailedly presents the design of the boundary scan testing system which is in accordance with ieee . 1149 . correspondingly two special - used data registers are added , one of which is the scanning chain register and the other is the child scanning chain control - register
    文中第二章按照ieee . 1149標(biāo)準(zhǔn)詳細(xì)設(shè)計(jì)了邊緣掃描測試系統(tǒng)，相應(yīng)增加了兩個專用數(shù)據(jù)寄存器，其中一個為掃描鏈寄存器，一個為掃描子鏈控制寄存器。
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